1. Field of the Invention
This invention relates to domino Static Random Access Memory (SRAM), and more particularly to an improved system for aligning the timing of the restore pulse on the local bit line pair with the timing of word and bit decode lines.
2. Description of Background
A static semiconductor memory typically includes six-transistor cell in which four transistors are configured as a cross-coupled latch for storing data. The remaining two transistors are used to obtain access to the memory cell. During a read access, differential data stored in the memory cell is transferred to the attached bit line pair. A sense amplifier senses the differential voltage that develops across the bit line pair. During a write access, data is written into the memory cell through the differential bit line pair. Typically, one side of the bit line pair is driven to a logic low level potential and the other side is driven to a high voltage level. The cells are arranged in an array that has a grid formed of bit lines and word lines, with the memory cells disposed at intersections of the bit lines and the word lines. The bit lines and the word lines are selectively asserted or negated to enable at least one cell to be read or written to.
As will be appreciated by those skilled in the art, in prior art domino SRAM design the cells are arranged into groups of cells, typically on the order of eight to sixteen cells per group. Each cell in a group is connected to a local bit line pair. The local bit line pair for each group of cells is coupled to a global bit line pair. Rather than use sense amplifier to detect a differential voltage when reading a cell, in a domino SRAM the local bit lines are pre-charged and discharged by the cell in a read operation, which discharge is detected and determines the state of the cell. The local bit line, the pre-charge means, and the detection means define a dynamic node of the domino SRAM. Domino SRAM of the type discussed here are explained in greater detail in U.S. Pat. Nos. 5,729,501, 6,058,065 and 6,657,886, which are incorporated herein by reference.
In domino SRAM array designs, the read or write operation is performed by initially pre-charging the bit lines and, after pre-charging, true and complement data is made available on the bit lines. In this scheme, the restore pulse to pre-charge the bit lines has to be very carefully aligned with the timing of the state of the word and bit decode lines in order to avoid a collision. The bit line restore pulse in a typical prior art design is generated by the local array clock signal. It does not have the same circuit delay as those in the word and bit decode paths. It is therefore difficult to line up the bit line restore pulse with the bit decode and word decode outputs to provide for a well synchronized operation.